Design of a CMOS Carry
Look-Ahead Adder for Self-Timed Circuits
Abstract
This paper presents the design of a 4-bit
carry look-ahead adder in differential cascode voltage switch (DCVS) logic
for application in self-timed circuits based on the recursive property of
the logic blocks, to extract multiple-outputs at complex gates, and on scaling
techniques in the transistors. The proposed adder reduces the routing area
and the number of transistors from the 256 of a conventional DCVS scheme to
190, thus producing a more compact circuit and a reduction in chip area of
30%.