P. Lamo, A. Pigazo, G.A. Ruiz, F.J. Azcondo, F. López
An Optimized Implementation of a Two-Sample Phase Locked Loop with Frequency Feedback for Single-Phase Sensorless Bridgeless PFC

IEEE 19th Workshop on Control and Modeling for Power Electronics (COMPEL), pp. 1-6, 2018

G.A. Ruiz, M. Granda.
Efficient low-power register array with transposed access mode

Microelectronics Journal, Vol. 45, Issue 4, pp. 463-467, April 2014

ISSN: 0026-2692. Published by ELSEVIER

DOI: 10.1016/j.mejo.2014.02.011

M.A. Manzano, J.A. Michell, G.A. Ruiz.
A High Throughput Processor chip for Transform and Quantization Coding in H.264/AVC.

Journal of Signal Processing Systems , Vol. 70, Issue 1, pp. 59-73, 2013

ISSN (Print): 1939-8018. ISSN (Online): 1939-8115. Published by Springer New York

DOI: 10.1007/s11265-012-0660-z  

G.A. Ruiz., J.A. Michell
Optimized Hardware Implementation for Forward Quantization of H.264/AVC

Journal of Signal Processing Systems , Vol. 72,  Issue 1, pp. 35-41, July 2013.

ISSN (Print): 1939-8018. ISSN (Online): 1939-8115. Published by Springer New York

DOI: 10.1007/s11265-012-0693-3

G.A. Ruiz, J.A. Michell.
Chapter 15, pp. 309-332: Variable Bit-Depth Processor for 8×8 Transform and Quantization Coding in H.264/AVC.

Book: Recent Advances on Video Coding. July 2011, Javier del Ser LLorente (Ed.).

ISBN: 978-953-307-181-7. Published by  INTECH (Open Access Publisher).  

G.A. Ruiz, M. Granda.

Efficient Canonic Signed Digit Recoding.

Microelectronics Journal, Vol. 42, Issue 9, pp. 1090-1097, September 2011.

ISSN: 0026-2692. Published by ELSEVIER

DOI: 10.1016/j.mejo.2011.06.006  

G.A. Ruiz, J.A. Michell.
An Efficient VLSI processor chip for Variable Block Size Integer Motion Estimation in H.264/AVC.

Signal Processing: Image Communication, Vol. 26, No. 6, pp. 289-303, July 2011.

ISSN: 0923-5965. Published by European Association for Signal Processing (EURASIP).

DOI: 10.1016/j.image.2011.04.006      

J.A. Michell, J.M. Solana, G.A. Ruiz.

A high-throughput ASIC processor for 8×8 transform coding in H.264/AVC.

Signal Processing: Image Communication, Vol. 26, No. 2, pp. 93-104, February 2011.

ISSN: 0923-5965. Published by European Association for Signal Processing (EURASIP).

DOI: 10.1016/j.image.2011.01.001   

G.A. Ruiz, J.A. Michell.

An Efficient VLSI Architecture of Fractional Motion Estimation in H.264 for HDTV.

Journal of Signal Processing Systems, Vol. 62, Issue 3, pp. 443-457,  2011.

ISSN (Print): 1939-8018. ISSN (Online): 1939-8115. Published by Springer New York

DOI: 10.1007/s11265-010-0475-8     

G.A. Ruiz, M. Granda.

Efficient implementation of 3X for radix-8 encoding.

Microelectronics Journal, Vol. 39, Issue 1, pp. 152-159. January 2008.

ISSN: 0026-2692. Published by ELSEVIER

DOI: 10.1016/j.mejo.2007.10.006  

G.A. Ruiz, M. Granda.

Efficient hardware implementation of 3X for radix-8 encoding.

Proc. of SPIE. Microtechnologies for the New Millennium 2007, vol. 6590, pp. 65901I-1 to 659001I-12. May 2007.

DOI: 10.1117/12.721489  

G.A. Ruiz, J.A. Michell.

Low-cost VLSI Architecture Design for Forward Quantization of H.264/AVC.

Proc. of SPIE. Microtechnologies for the New Millennium 2007, vol. 6590, pp. 65900Y-1 to 65900P-12. May 2007.

DOI: 10.1117/12.721493

J. García, J.A. Michell, G.A. Ruiz, A.M. Burón.

FPGA realization of a Split Radix FFT processor.

Proc. of SPIE. Microtechnologies for the New Millennium 2007, vol. 6590, pp. 65900P-1 to 65900P-11. May 2007. 

DOI: 10.1117/12.721975 

G.A. Ruiz, J.A. Michell, A.M. Burón.

High Throughput Parallel-Pipeline 2D DCT/IDCT Processor chip.

Journal of VLSI Signal processing Systems for Signal, Image and Video Technology, Vol. 45, pp. 161-175, Dec. 2006.

(Now called Journal of Signal Processing Systems)

ISSN (Print): 1939-8018. ISSN (Online): 1939-8115. Published by Springer New York

DOI: 10.1007/s11265-006-9764-7      

G.A. Ruiz, J.A. Michell, A.M. Burón.

High Throughput 2D  DCT/IDCT Processor for video coding.

IEEE  International Conference on Image Processing (ICIP), pp. III-1036/39, September 2005.

ISBN: 0-7803-9134-9

DOI: 10.1109/ICIP.2005.1530572    

G.A. Ruiz, J.A. Michell, A.M. Burón.

Parallel-pipeline 2D DCT/IDCT processor architecture.

Microtechnologies for the New Millennium, pp. 774-784, Mayo 2005.

G.A. Ruiz, J.A. Michell, A.M. Burón.

Parallel-Pipeline 8x8 Forward 2-D ICT Processor Chip for Image Coding.

IEEE Trans. on. Signal Processing, vol. 53, issue 2, pp. 714-723, Feb. 2005.

ISSN: 1053-587X. Published by Institute of Electrical and Electronics Engineers.

DOI: 10.1109/TSP.2004.840682    

G.A. Ruiz, M. Granda.

An Area-Efficient Static CMOS Carry-Select Adder Based on a Compact Carry Look-ahead Unit.

Microelectronics Journal, vol. 35, issue 12, pp. 939-944, December 2004.

ISSN: 0026-2692. Published by ELSEVIER

DOI: 10.1016/j.mejo.2004.09.002 

J.A. Michell, G.A. Ruiz, A.M. Burón.

Parallel-pipelined Architecture for 2-D ICT VLSI Implementation.

IEEE International Conference on Image Processing, Barcelona, Spain, pp III-89 to III-92. September 14-17, 2003.

ISSN :  1522-4880. ISBN: 0-7803-7750-8.

DOI: 10.1109/ICIP.2003.1247188   

G.A. Ruiz, J.A. Michell, A.M. Burón, J.M. Solana, M.A. Manzano, J. Díaz.

A Integer Cosine Transform Chip Design for Image Compression.

Proceedings of SPIE - The International Society for Optical Engineering, Vol. 5117, pp.33-41, 2003.

DOI: 10.1117/12.49877    

G.A. Ruiz, M.A. Manzano.

Self-timed Multiplier Based on Canonical Signed-Digit Recoding.

IEE Proceedings-Circuits, Devices and Systems,  Vol 148, Issue 05, pp 235-241, October 2001.

ISSN: 1350-2409. Published by Institution of Engineering and Technology.

DOI: 10.1049/ip-cds:20010524 

G.A. Ruiz, M.A. Manzano.

Compact 32-bit CMOS adder in Multiple-Output DCVS Logic for Self-Timed Circuits.

IEE Proceedings-Circuits, Devices and Systems,Vol. 144, Issue 3,  pp 183-188, June 2000.

ISSN: 1350-2409. Published by Institution of Engineering and Technology.

DOI: 10.1049/ip-cds:20000381 

J.L. Sanz, R.B. Barreiro, L. Cayon, E. Martinez-Gonzalez, G.A. Ruiz, J. Diaz, F. Argueso  and L. Toffolatti.

Analysing Planck-like data with wavelets.

Astrophysical Letters and Communications, Vol. 37, pp 341-348, 2000.

ISSN: 0888-6512.

J.L. Sanz, R.B. Barreiro, L. Cayon, E. Martinez-Gonzalez, G.A. Ruiz, J. Diaz, F. Argueso, J. Silk, L. Toffolatti.

Analysis of CMB maps with 2D wavelets.

Astronomy and Astrophysics, Suppl. Ser., Vol. 140, pp. 99-105, November 1999.

ISSN (Print Edition): 0004-6361. ISSN (Electronic Edition): 1432-0746. Published by: EDP Sciences.

DOI: 10.1051/aas:1999119  

G.A. Ruiz.

4bit CLA-based conversion from redundant to binary representation for CMOS simple and multi-output implementations.

Electronics Letters, Vol 35, N. 4, pp 281-283, 18th February 1999.

ISSN: 0013-5194. Published by Institution of Engineering and Technology.

DOI: 10.1049/el:19990232  

G.A. Ruiz.

Electrical Simulator for Bridging and Floating Failures in MOS Digital Circuits.

International Journal of Modelling and Simulation, Vol 19, No 1, pp 77-84,1999.

ISSN (Online): 1925-7082. ISSN (Hardcopy): 0228-6203. Published by Acta Press.

 Abstract.

G.A. Ruiz.

Evaluation of three 32-bit CMOS Adders in DCVS logic for Self-Timed Circuits.

IEEE J. Solid-State Circuits.Vol. 33, No. 4, pp 604-613, April 1998.

ISSN: 0018-9200. Published by Institute of Electrical and Electronics Engineers.

DOI: 10.1109/4.663566    

G.A. Ruiz, J.A. Michell.

Memory Efficient Programmable Processor Chip for Inverse Haar Transform.

IEEE Trans. on Signal Processing. Vol. 46, No. 1, pp 263-268, January 1998.

ISSN: 1053-587X. Published by Institute of Electrical and Electronics Engineers.

DOI: 10.1109/78.651233   

G.A. Ruiz.

New Static Multi-Output Carry Lookahead CMOS Adders.

IEE Proceedings-Circuits, Devices and Systems,Vol. 144, Issue 6,  pp 350-355, December 1997.

ISSN: 1350-2409. Published by Institution of Engineering and Technology.

DOI: 10.1049/ip-cds:19971445  

G.A. Ruiz.

Design of a CMOS Carry Look-Ahead Adder for Self-Timed Circuits.

International Journal of Modelling and Simulation, Issue 4, pp. 257-260, 1997.

ISSN (Online): 1925-7082. ISSN (Hardcopy): 0228-6203. Published by Acta Press.

Abstract.

 G.A. Ruiz.

Compact Four Bit Carry Look-Ahead CMOS Adder in Multi-Output DCVS Logic.

Electronics Letters, Vol 32, N. 17, pp 1556-1557, 15th August 1996.

ISSN: 0013-5194. Published by Institution of Engineering and Technology.

DOI: 10.1049/el:19961082  

G. Ruiz, D. Herrero, J.A. Michell, A.M. Burón.

Electrical Simulator for Gate Oxide Shorts and Resistive Shorts in MOS Digital Circuits.

Proc. of the IX IASTED International Conference Applied Informatics, pp. 91 - 94, May 1993.

ISBN 0-88986-175-7.Published by ACTA PRESS.

G. Ruiz, J.A. Michell, A.M. Burón, J.M. Solana.

Diseño ASIC de la "Sección Bidimensional" del Algoritmo 2D FHT para Aplicaciones en Tiempo Real.

Microelectrónica 92: Tecnologías, Diseño, Aplicaciones, pp. 199-207, 1993.

ISBN 84-8102-014-1.Servicio de Publicaciones de la Universidad de Cantabria.

G.A. Ruiz, J.A. Michell, A.M. Burón.

Switch-level Fault Detection and Diagnosis Environment for MOS Digital Circuits using Spectral Techniques.

IEE-E Computers and Digital Techniques. Vol 139, No 4, pp. 293-307, July 1992.

ISSN: 1751-8601. Published by Institution of Engineering and Technology. 

G. Ruiz, J.A. Michell, A.M. Burón.

Sistema de Ayuda al Test de Circuitos Digitales MOS Basado en Técnicas Espectrales.

Actas del VI Congreso de Diseño de Circuitos Integrados, Universidad de Cantabria, pp. 465-470. Noviembre 1991.

J.A. Michell, A.M. Burón, J.M. Solana, G. Ruiz.

A Three Processor Parallel-Pipelined Architecture of the 2D-FHT at Video Rates.

Proceedings of the Fourth ISMM/IASTED International Conference Parallel and Distributed Computing and Systems, pp. 170-174, October 1991.

ISBN 0-88986-159-5. Published by ACTA PRESS.

G. Ruiz, J.A. Michell, A.M. Burón.

Automatic Test Vector Set Generation in the Spectral Testing of Sequential Circuits.

Proceedings of the 40th ISMM International Symposium: Mini and Microcomputers and their Applications, pp. 55 - 58, June 1990.

ISBN 0-88986-150-1. Published by ACTA PRESS.

J.A. Michell, A.M. Burón, J.M. Solana, G. Ruiz.

VLSI Data-Path Structure for a Pipelined 2D-FHT Implementation.

SIGNAL PROCESSING V: Theories and Applications.3, pp. 1575-1578, 1990.

ISBN 0-444-88636-2. Published by Elsevier Science Publishers B.V.

G. Ruiz, J.A. Michell, A.M. Burón.

Generador Automático de Secuencias de Test para la Verificación Espectral de Circuitos Secuenciales.

Comunicaciones de la V Escuela de Microelectrónica, Universidad de Granada, pp. 301-304, 1990.

ISBN 84-338-1172-X.

A.M. Burón, J.A. Michell, J.M. Solana, G. Ruiz.

An On-Line Implementation of the 2D-FHT at Megahertz Rates.

Proceedings of the International Conference on Signal Processing, Pekin (China), pp. 543-546, 1990.

Published by International Academic Publishers.

G. Ruiz, J.A. Michell, A.M. Burón.

Herramientas de Ayuda a la Diagnosis de Fallos Físicos en Circuitos Secuenciales MOS/CMOS Via Análisis Espectral.

Proceedings V Jornadas de Diseño de Circuitos Integrados, Universidad de Sevilla, pp. 333-340., December 1989.

ISBN 84-7405-472-9.

G. Ruiz, J.A. Michell, A.M. Burón.

An Approach to the Spectral Testing of MOS Sequential Circuits.

Proceedings of the 39th ISMM International Conference: Mini and Microcomputers and their Applications, pp. 109-112, June 1989.

ISBN 0-88986-123-4. Published by ACTA PRESS.

G. Ruiz, J.A. Michell, A.M. Burón.

Diagnosis of Stuck-Open Faults in CMOS by Spectral Techniques with Pseudorandom Excitation.

Proceedings of the Seventh IASTED International Symposium on Applied Informatics, pp. 89-92, February 1989.

ISBN 0-88986-117-X. Publised by ACTA PRESS.

G. Ruiz, J.A. Michell, A.M. Burón.

Fault Detection and Diagnosis for MOS Circuits from Haar & Walsh Spectrum Analysis: On the Fault Coverage of Haar Reduced Analysis.

Proceedings of the 3rd. International Workshop On Spectral Techniques, University of Dortmund, pp. 97-106, October 1988.

ISSN 0933-6192

G. Ruiz, A.M. Burón, J.A. Michell

NMOS & CMOS Physical Faults Diagnosis by Spectral Techniques: Simulation and Associated Tools.

Proceedings of the IEEE Workshop on Languages for Automation. pp. 191-194.,August 1987.

ISBN 0-8186-0797-1. Edited by Computer Society Press of the IEEE