Electrical Simulator for Bridging and Floating Failures in MOS Digital Circuits
Abstract
This paper presents
an electrical simulator oriented towards treating bridging and floating
line failures in MOS digital circuits. This simulator makes it possible to
obtain the time response, power supply current and the degradation of the
voltage logic levels, which are in fact the parameters most sensitive to
the presence of these failures. Its most important features are: the use
of a linear model of MOS transistors based on the analytic equations SPICE
(LEVEL=2); the utilization of the simple Euler Algorithm with variable step
to solve the differential equations of the circuit; and the incorporation
of local relaxation algorithms to reduce the number of nodes to be processed.
The simulation results are similar to those obtained with SPICE but with
computation times that are one to two orders of magnitude smaller.